Logic devices such as digital signal processors, microprocessors, programmable circuit devices, and Application Specific Integrated Circuits (ASICs) contain many millions of transistors switching at very high frequencies. Such devices consume large amounts of power, requiring 200 watts or more. Power P may be defined as the voltage V between the power and ground buses of a logic device multiplied by the current I entering the logic device through the power bus and exiting the logic device through the ground bus, P=V×I. The logic device is contained in a logic device package that contains power and ground planes that connect logic device power and ground buses to the power supply. The logic device power and ground buses provide voltage and current to the subcircuits within the logic device. At any given time, the logic device through the power and ground planes and buses may draw many amperes of current from the power supply at high voltages.
Software instructions executing on the logic device can cause vast swings in the current needed by the logic device. Depending on the instruction, whole subcircuits in the logic device may turn on or off, creating large shifts in the current through the power and ground planes and buses. As a result of the resistance and inductance in the power and ground planes and buses, these large current draws can result in voltage noise that can lead to malfunction of the logic device. Such voltage noise on the power and ground planes and buses is generally known as power bounce or ground bounce.
Voltage bounce on the power and ground planes and buses may also be caused by the switching of high speed input/output (I/O) buffer circuitry in the logic device as described by Christopher W. Zell and Douglas J. Hamilton, “A Simple Simultaneous Switching Noise (SSN) Modeling and Simulation Methodology,” IEEE 5th Topical Meeting of Electrical Performance of Electronic Packaging, pp. 129-131, Oct. 28-30, 1996. I/O buffer circuitry sends and receives signals between the logic device and other integrated circuit devices on a circuit board. The I/O buffer circuitry must be able to switch from a high state to a low state and from a low state to a high state at very high speeds. The high state and low state may represent binary values of one and zero, respectively. Large transistors capable of driving high currents for high speed signal transmission and switching are present in the I/O buffer circuitry. As the switching speed is increased more and more by increasing the clock speed and transition rate of the I/O buffer circuitry, more voltage bounce is generated.
Bounce on the power and ground planes and buses in a logic device may be reduced in a variety of ways. Bypass capacitors are commonly used to decouple the power and ground planes. Such bypass capacitors are very effective for low currents and for frequencies up to about 1 GHz. However, high performance logic devices such as microprocessors may require upwards of 30 amperes of current for various subsystems. Such high currents and corresponding voltages cannot easily be filtered by the bypass capacitors to minimize power and ground bounce.
Power and ground bounce may also be reduced by distributing multiple power and ground planes and buses over different areas of the logic device and package. Power and ground bounce caused by the I/O buffer circuitry may be reduced by placing the circuitry near bonding pads along the edge of the logic device to reduce the length of current travel and thus reduce inductance. Short wire bonds connecting the logic device bonding pads to lead fingers on the circuit board may further reduce power and ground bounce caused by the inductance of the wire bonds. Flip chip packaging technology may also be used to minimize power and ground bounce. Improved I/O buffer circuitry switching at different times may also reduce power and ground bounce. The techniques described above require complex and time consuming design of the logic device circuitry and do not eliminate the power and ground bounce. Thus, there has been a longfelt need for an improved method and apparatus to minimize power and ground bounce in the logic device.